As feature sizes in integrated circuit technology decrease to nanometer scale, the impact of process and operational parameter variations in circuit performance is significant. Therefore, it becomes extremely relevant to be able to accurately identify, for a given circuit, what parameter settings (commonly designated by corners) will degrade its performance the most. Important performance metrics are timing and power. In this context, our invention provides a run time and memory efficient way of computing the set of assignments for process and operational parameters that will produce the critical timing conditions on a given digital integrated circuit.
Prior solutions rely on exhaustive approaches that explicitly explore the entire solution space, by evaluating every possible solution, and choosing the one that produces the critical timing conditions.
Exhaustive approaches are slow, because in most cases the size of the solution space is exponential (either in the number of paths or in the number of parameters), and therefore an explicit enumeration and evaluation of every possible solution is computationally too expensive to permit any practical use, even in moderately sized circuits.